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Device and Transistor Level Circuit Performance Analysis of Nanoscale Mosfet

Ooi, Chek Yee (2019) Device and Transistor Level Circuit Performance Analysis of Nanoscale Mosfet. PhD thesis, UTAR.

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    When nano-MOSFET structural dimension is downscaled to nanometer regime, quantum effects become obvious. This small channel length nano-MOSFET reduces electron transit time from source to drain. Owing to small dimension, its smaller capacitance would result lower power dissipation. When applying this nano-MOSFETs in designing resistive loaded logic gates, lower power dissipation high speed logic gates are produced. The first objective of this thesis is to prove the optimized parameters of n-channel nano-MOSFET formulated by Purdue University using nanoMOS software also developed by Purdue University. The nano-MOSFET parameters involved include channel length, temperature, gate contact work function, gate underlap, intrinsic channel and gate length. They are optimized by characterizing the electrical quantities such as subband energy levels, electron density profile, transmission coefficient, leakage current and threshold voltage aiming to produce low potential barrier height, unity transmission coefficient, low leakage current and small threshold voltage. The second objective is to characterize the dc and ac parameters for the logic gates designed with this optimized parameters n-channel nano-MOSFET by simulation using WinSpice and HSPICE simulators. The logic gates timing characteristics such as risetime, fall time and propagation delay are evaluated by using simulators. The power dissipation reduction is observed from simulation results. This research project has successfully achieved the objectives. The final optimized parameters of the nano-MOSFET are channel thickness of 1.5 nm, temperature of 300 K, gate contact work function of 4.188 eV, no gate underlap, gate length of 10 nm and intrinsic channel. The criteria used to justify the above device optimization are low threshold voltage of 0.20 V, ballistic efficiency of 0.96 and low leakage current of 5.312x10-2 μA/μm. The ac parameters mainly rise time, fall time and propagation delay of the logic circuits have been analyzed and the dc parameters analysed are VOH, VOL, VIH, VIL, VM, VLS, VTW,VNMH, VNML, VNSH, VNSL, VNIH and VNIL. The value of lower power dissipation and shorter propagation delay of logic gates achieved are in the range of microwatts (μW) and femtosecond (fs), respectively. In future work, the similar study on the characteristics p-channel nano- MOSFET can be done so that it can combine with n-channel nano-MOSFET to design and characterize the nano-complimentary MOSFET (nano-CMOS) logic gates.

    Item Type: Final Year Project / Dissertation / Thesis (PhD thesis)
    Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
    Divisions: Institute of Postgraduate Studies & Research > Lee Kong Chian Faculty of Engineering and Science (LKCFES) - Sg. Long Campus > Doctor of Philosophy in Engineering
    Depositing User: Sg Long Library
    Date Deposited: 04 Dec 2019 17:30
    Last Modified: 04 Dec 2019 19:40
    URI: http://eprints.utar.edu.my/id/eprint/3602

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