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Design and development of memory system for 32 bits 5-stage pipelined processor: Main memory (DRAM) integration.

Kim, Yuh Chang (2013) Design and development of memory system for 32 bits 5-stage pipelined processor: Main memory (DRAM) integration. Final Year Project, UTAR.

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    Item Type: Final Year Project / Dissertation / Thesis (Final Year Project)
    Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
    Divisions: Faculty of Information and Communication Technology > Bachelor of Information Technology (Honours) Computer Engineering
    Depositing User: ML Main Library
    Date Deposited: 12 Sep 2013 12:34
    Last Modified: 12 Sep 2013 12:34
    URI: http://eprints.utar.edu.my/id/eprint/947

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