Items where Subject is "T Technology > TF Railroad engineering and operation"
Group by: Creators | Item Type Number of items at this level: 5.
CChoo, Jia Zheng (2022) Design of a 7-Stage pipeline RISC processor (MEM STAGE). Final Year Project, UTAR. EEr, Pei Qing (2022) The development of an RTOS for the 5-Stage pipeline RISC32 microprocessor. Final Year Project, UTAR. LLeong, Kar Yong (2022) Clock domain crossing design for 5-Stage Pipeline RISC32. Final Year Project, UTAR. TTan, E-Chian (2022) Design of a direct memory access module for 32-BIT RISC32 processor. Final Year Project, UTAR. Teo, Sei Hau (2022) RISC32-E cryptography performance evaluation. Final Year Project, UTAR. |