Items where Subject is "T Technology > TG Bridge engineering"
Group by: Creators | Item Type Number of items at this level: 9.
Final Year Project / Dissertation / ThesisChoo, Jia Zheng (2022) Design of a 7-Stage pipeline RISC processor (MEM STAGE). Final Year Project, UTAR. Er, Pei Qing (2022) The development of an RTOS for the 5-Stage pipeline RISC32 microprocessor. Final Year Project, UTAR. Ho, Yun Li (2013) Bi-objective optimization of exclusive bus lane allocation and scheduling problem in cities. Master dissertation/thesis, UTAR. Leong, Kar Yong (2022) Clock domain crossing design for 5-Stage Pipeline RISC32. Final Year Project, UTAR. Seah, Ni Xuan (2022) Wireless predictive text entry system for the handicapped. Final Year Project, UTAR. Tan, E-Chian (2022) Design of a direct memory access module for 32-BIT RISC32 processor. Final Year Project, UTAR. Tan, Yan kai (2022) Design of an ADC controller for 5-stage pipeline RISC32 microprocessor. Final Year Project, UTAR. Teo, Sei Hau (2022) RISC32-E cryptography performance evaluation. Final Year Project, UTAR. Yong, Tze Liang (2022) Smart underground cylindrical parking system. Final Year Project, UTAR. |
