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The design and development of a branch target buffer based on a 2-bit prediction scheme for a 32-bit RISC32 pipeline processor

Ho, Ming Cheng (2013) The design and development of a branch target buffer based on a 2-bit prediction scheme for a 32-bit RISC32 pipeline processor. Final Year Project, UTAR.

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    Item Type: Final Year Project / Dissertation / Thesis (Final Year Project)
    Subjects: T Technology > T Technology (General)
    Divisions: Faculty of Information and Communication Technology > Bachelor of Information Technology (Honours) Computer Engineering
    Depositing User: ML Main Library
    Date Deposited: 01 Jul 2014 07:12
    Last Modified: 07 Jul 2014 13:10
    URI: http://eprints.utar.edu.my/id/eprint/1176

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