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Circuit Under Pad Programmable and Slew Rate Controlled Output Buffer Design

Chai, Wei Qian (2016) Circuit Under Pad Programmable and Slew Rate Controlled Output Buffer Design. Final Year Project, UTAR.

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    Abstract

    The use of resistive, capacitive or inductive external loads will make the integrated circuits more susceptible to the output ringing problem if more than one output is switching simultaneously. In order to reduce this signal swing problem, limitation of the maximum rate of change of output voltage, which is also known as output slew rate, is preferred. Therefore, the purpose of this study is to design the output buffer as an interface between the integrated circuit and external loads for controlling the slew rate with slow, mid-range and fast slew rate design. The output buffer with slew rate controlled must act fast enough to meet the speed requirement of the system while minimizing the noise problems. Besides, the output loading condition may vary for different types of applications. This introduces different drive strengths used to drive different capacitive loads. In view of this, the project is also focusing on the design of output buffer such that it is featured with programmable drive strength to enable the users to select the desired operating mode that best suits their applications. The drive strength capability is designed for 2-mA, 4-mA, 6-mAand 8-mA. The designs are featured with circuit under pad structure and using SilTerra C18G process with 0.18µm low power process technology. The performances of C.U.P. programmable and slew rate controlled output buffers are evaluated.

    Item Type: Final Year Project / Dissertation / Thesis (Final Year Project)
    Subjects: T Technology > T Technology (General)
    Divisions: Faculty of Engineering And Green Technology > Bachelor of Engineering (Hons) Electronic Engineering
    Depositing User: ML Main Library
    Date Deposited: 29 Aug 2016 10:16
    Last Modified: 15 Aug 2019 13:26
    URI: http://eprints.utar.edu.my/id/eprint/2036

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