Implementation of VLSI design flow for MIPS-based SOC

Lee, Zhao Min (2022) Implementation of VLSI design flow for MIPS-based SOC. Final Year Project, UTAR.

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Abstract

MIPS is a VLSI microprocessor based on RISC architecture which focuses on increasing the performance with the trade-off of its hardware and instruction complexity. VLSI design flow is the common design methodology used for integrated circuit design. The two phases in the VLSI design flow are front-end design and back end design. The complete VLSI design flow is implemented to produce a MIPS-based SoC. EDA tools from Synopsys Inc are used in this project to carry out the processes including logic synthesis, floorplanning, placement, routing, physical verification, and others. The use of EDA tools could shorten the long VLSI design cycle with design automation. The MIPS design is optimised to reduce the design cost and improve the performance of the design. Synopsys Design Compiler is used for the front-end design while Synopsys IC compiler is used to complete the back-end design. The final layout produced from the IC compiler is able to pass the timing and physicals verifications.

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