Loh, Jing En (2023) Back End Design (Automatic Place and Route) of RISC-V Processor using IC Compiler. Master dissertation/thesis, UTAR.
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Abstract
This research paper focuses on the development of an Automatic Place and Route (APR) methodology for the RISC-V processor design using the IC Compiler tool. The proposed methodology is aimed at achieving good Quality of Results (QoR) for different technology nodes, including 32nm and 90nm. The paper provides a detailed analysis of the QoR obtained for each technology node and compares the results obtained with each other. On top of that, the effect of clock period on the design quality is also analyzed. The methodology used for the design flow and the physical implementation process of the design using IC Compiler are all explained in detail. The experimental results demonstrate the effectiveness of the proposed methodology in achieving good QoR for RISC-V processor designs.
| Item Type: | Final Year Project / Dissertation / Thesis (Master dissertation/thesis) |
|---|---|
| Subjects: | T Technology > T Technology (General) T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Institute of Postgraduate Studies & Research > Faculty of Engineering and Green Technology (FEGT) - Kampar Campus > Master of Engineering in Electronic System |
| Depositing User: | ML Main Library |
| Date Deposited: | 01 Jan 2024 20:47 |
| Last Modified: | 01 Jan 2024 20:47 |
| URI: | http://eprints.utar.edu.my/id/eprint/5959 |
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