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Design and simulate RISC-V processor using verilog

Ngu, David Teck Joung (2023) Design and simulate RISC-V processor using verilog. Master dissertation/thesis, UTAR.

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    In this project, RISC-V processor is designed and simulated using Verilog. The design of RISC-V processor provides an alternative for software and hardware design to the computer designers as it provides free and open instruction set architecture (ISA). Besides, the designed RISC-V processor will be using 5- stage pipeline techniques to improve the overall performance of the processor. The project is started by implementing several main modules, such as alu, aludec, maindec, imem, dmem, regfile, pc_mux, result_mux, pipeline register (IF/ID, ID/IEx, IEx/IMem, and IMem/IW), forwardMuxA and forwardMuxB. Besides, hazard unit is implemented into the design to mitigate hazard conditions. The functionality of these modules was simulated and verified by using ModelSim software. Then, the modules were integrated into a main module to form a riscv_pip_27 module. A simple testbench is written to verify the functionality of the RISC-V processor.

    Item Type: Final Year Project / Dissertation / Thesis (Master dissertation/thesis)
    Subjects: T Technology > T Technology (General)
    T Technology > TK Electrical engineering. Electronics Nuclear engineering
    Divisions: Institute of Postgraduate Studies & Research > Faculty of Engineering and Green Technology (FEGT) - Kampar Campus > Master of Engineering in Electronic System
    Depositing User: ML Main Library
    Date Deposited: 01 Jan 2024 20:58
    Last Modified: 01 Jan 2024 20:58
    URI: http://eprints.utar.edu.my/id/eprint/5966

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