The development of an exception scheme for 5-stage pipeline RISC processor

Goh, Jia Sheng (2019) The development of an exception scheme for 5-stage pipeline RISC processor. Final Year Project, UTAR.

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Abstract

Exception classified into two types, which are the internal exception and external exception. Normally, we called internal exception as trap and External exception as interrupt. Exception makes the 5-stage pipeline processor more complicated because the exception is difficult to handle in pipeline processor due the overlapping instruction characteristics. The exception will cause abnormal program flow, and when exception occur, we need to provide some operation to overcome the problem. The IoT SoC processor will used for this project purpose. Up-to-date, the processor has a few I/O modules integrated namely the UART, GPIO and SPI. It also has a co-processor and programmable interrupt controller to handle the exceptions. The handling of the exceptions was half-planned, however, not up to a high confidence level. Therefore, this project is initiated to develop an exception handling scheme to handle the multiple interrupt (including nested interrupts) occurrence. Interrupt can occur at any time, and the timing to capture the data is critical. For example, when the UART and SPI received the data at the same time, both module will raise the interrupt flag concurrently. Therefore, we need a plan to schedule which one need to be serve first. The situation is further complicated when the multiple nested interrupts and traps occurs concurrently. With the availability of the exception-handling scheme, it is straightforward to resolve the conflicts among the mentioned exceptions. In addition, it will be easier to plan ahead to integrate new devices without having to worry about buggy exception handling.

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