Front end design (logic synthesis) of Risc-V processor using design compiler

Koay, Yenn Nee (2023) Front end design (logic synthesis) of Risc-V processor using design compiler. Master dissertation/thesis, UTAR.

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Abstract

Modern microprocessors depend on Design Compiler's logic synthesis of RISC-V processor Front-Ends. This study examines the synthesis process for a 14nm, 32nm, or 90nm RISC-V processor at clock periods from 0 to 5 nanoseconds. The analysis begins with design constraints, including clock frequency, area limits, and timing requirements for each technological node. The Design Compiler tool converts the Register Transfer Level (RTL) description of the RISC-V processor into a gate-level netlist. The design's applicability to 14nm, 32nm, and 90nm process nodes is assessed during synthesis by linking technology libraries. After synthesizing designs, performance indicators like timing closure, clock period needs, and slack margins across technology nodes are analyzed. To understand the processor's power consumption, power analysis is done at different clock intervals. To optimize designs at each technological node, processor area consumption is analyzed. The research examines 14nm, 32nm, and 90nm front-end design performances using clock durations from 0 to 5 nanoseconds. These different manufacturing technologies and operating circumstances provide vital insights about the processor's performance, power efficiency, and space usage. With this knowledge, designers can choose technology, clock frequency, and architectural changes to suit future computing system demands. This research helps designers construct high-performance, energy efficient, area-optimized RISC-V processors that are adaptable to different technology nodes and clock periods. The study advances front-end design in microprocessor development, enabling the design of cutting-edge processors that excel across varied technology landscapes and operating scenarios.

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