Clock domain crossing design for 5-Stage Pipeline RISC32

Leong, Kar Yong (2022) Clock domain crossing design for 5-Stage Pipeline RISC32. Final Year Project, UTAR.

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Abstract

This project is about the clock domain crossing (CDC) circuit design and implementation in RISC32 for academic purposes. Due to the I/O system usually requires a lower frequency to operate as compared to the CPU clock, the CDC circuit being implemented in RISC32 can allow its I/O system to work in different frequencies, thus it can reduce the total power consumption. The development of this project will begin with the design of the CDC unit and the asynchronous FIFO block after reviewing the technologies available for CDC circuit design. The RTL design flow will be used throughout the project development and the micro-architectural level design will be focused more as the asynchronous FIFO block to be designed is at the block level. The internal sub-blocks of the asynchronous FIFO block will be modeled by using Verilog HDL before they are integrated into higher block levels. The specifications of the CDC unit and its internal blocks will be functionally verified by writing testbenches in Verilog HDL. The CDC unit will be integrated into the RISC32 processor and tested again to verify whether the design of the block is functionally correct and works as desired. In short, a piece of software containing the design of blocks in CDC circuit and their testbenches written using Verilog code and simulation results are expected to be delivered at the end of the project.

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